> For the complete documentation index, see [llms.txt](https://docs.augelab.com/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://docs.augelab.com/function-blocks/blocks-reference/input-output/data-inputs/pwm-pulse-width-modulation.md).

# PWM (Pulse Width Modulation)

This function block generates an artificial pulse-width-modulated boolean signal you can use to simulate or drive timed triggers. Use it to create repeating on/off signals either by time (seconds) or by sample counts (discrete steps).

## 📥 Inputs <a href="#inputs" id="inputs"></a>

This function block does not have any inputs.

## 📤 Outputs <a href="#outputs" id="outputs"></a>

`Boolean` The periodic True/False signal produced according to the configured mode and timings.

## 🕹️ Controls <a href="#controls" id="controls"></a>

`Interval` Enter the total period of one cycle. In Time mode this is in seconds. In Sample mode this is in number of samples/steps.

`Up Duration` Enter how long the output stays True within each cycle. Units match the selected mode (seconds or samples).

`Time mode` Toggle between Seconds (time-based mode) and Samples (sample-count mode).

## 🎨 Features <a href="#features" id="features"></a>

* Time-based PWM mode for real-time periodic signals.
* Sample-based PWM mode for step-driven or frame-synchronized signals.
* Adjustable duty cycle via `Interval` and `Up Duration` controls.
* Simple boolean output that is easy to combine with logic and output blocks.

## 📝 Usage Instructions <a href="#usage" id="usage"></a>

1. Choose the operating mode with `Time mode`.
2. Set `Interval` to define the full cycle length.
3. Set `Up Duration` to define the active (True) portion of each cycle. Ensure `Up Duration` is less than or equal to `Interval`.
4. Connect the `Boolean` output to any block that consumes a check / boolean signal (for example `Led Output` to visualize, or logic blocks to gate other behaviors).

## 📊 Evaluation <a href="#evaluation" id="evaluation"></a>

At runtime the block produces a repeated True/False pattern. In Time mode the pattern follows real seconds. In Sample mode the pattern advances with each run/step. The output duty cycle equals (`Up Duration` ÷ `Interval`).

## 💡 Tips and Tricks <a href="#tips-and-tricks" id="tips-and-tricks"></a>

* Visualize the signal using `Scope` to verify timing and duty cycle in real time.
* Use `Rising Edge` to detect transitions and trigger single-shot actions on the leading edge.
* Count pulses with `Counter` to measure occurrences or drive batch operations.
* Combine with `And` or `Or` to gate the PWM signal with other conditions (for example a manual `Logic Input`).
* Use `Delay Step`, `ON Delay` or `OFF Delay` blocks to shape or debounce transitions.
* Persist or freeze signals with `Data Memory` when you need a stable value between updates.

## 🛠️ Troubleshooting <a href="#troubleshooting" id="troubleshooting"></a>

* Output always True or always False
  * Check that `Up Duration` and `Interval` are set correctly and that the selected `Time mode` matches your expected units (seconds vs samples).
* Timing seems off in Time mode
  * Verify that the host system clock is running and that other blocks are not blocking execution. Use `Scope` to confirm real timings.
* Sample mode does not advance as expected
  * Ensure the system is producing steps/samples (the run loop or upstream blocks must provide iterations). Use `Counter` or `Cycle Timer` to inspect step progress.
